Observing test response of embedded cores through surrounding logic

This paper addresses the problem of observing the test response of an embedded intellectual property core. For the core test set specified by the core vendor, the logic surrounding the core can mask errors at the output of the core such that faults in the core may go undetected. For intellectual property cores where there is no knowledge of the internal structure of the core (i.e., the core is a black box), no assumptions can be made about what errors the faults in the core may cause at the core outputs. All possible errors at the core outputs must be observable. Existing observation point insertion techniques (all of which are based on a fault model and require knowledge of the circuit structure) cannot be used. The conventional solution to this problem is to directly observe the core outputs by either multiplexing them to chip pins or placing a boundary scan around the core. This paper describes necessary and sufficient conditions (assuming no knowledge of the internal structure of the core) for guaranteeing that all errors at the outputs of the core can be observed through logic surrounding the core (combinational or sequential). A systematic method for inserting a minimal set of observation points necessary for testing a core (with either parallel or serial access) is presented.